Two of the important driving forces in the progress of semiconductor integrated circuits are reduction in the size of individual devices so the packing density per chip site increases, and increase in the size of the wafers used in integrated circuit production so the number of chip sites per wafer increases. Both forces impact directly the cost per integrated circuit device. A limiting factor on the continuing evolution of both of these forces is the increasing role of surface variations or undulations due to bowing of the wafers. The most consequential effect of these variations is on lithographic processing because the projected lithographic image does not have sufficient depth of field to provide acuity over the whole wafer. Means have been devised to refocus the image at each site of the wafer using a wafer stepper lithography apparatus, but the depth of the wafer plane may vary over a distance corresponding to a single chip site. It is intuitively evident that increasing the diameter of the wafer in order to increase the number of chip sites and reduce the cost per chip for a given processed wafer cost will further complicate the bowing and warping problem.
Wafer warpage caused by thermomechanical effects during processing also contributes to the problem just described. Differential strains of other kinds will also aggravate the problem. One of these is the lattice strain produced by the introduction of large quantities of dopants into the substrate onto which an epitaxial layer is grown. The usual objective in epitaxial structures is to make a relatively lightly doped or high resistivity layer, typically 1-10 ohm cm, on a relatively heavily doped or conductive substrate, typically 0.1 to 0.002 ohm cm. Commonly the approach is to deposit a lightly doped p-type layer on a heavily boron doped substrate. These structures tend to exhibit bowing due to the crystal lattice mismatch between the heavily born doped substrate and the more nearly intrinsic silicon epitaxial layer. The substitution of boron in large concentrations into the substrate crystal shrinks the lattice parameter of the substrate. The deposition of relatively pure silicon on this substrate causes stresses to develop in the epitaxial layer. As the layer becomes thicker these stresses develop sufficiently to cause strains in the layer which in turn cause bowing of the epitaxial wafer.